The present invention relates to copper (Cu) and/or Cu alloy metallization in semiconductor devices, particularly to reliably capping Cu or Cu alloy interconnects. The present invention is applicable to manufacturing high speed integrated circuits having submicron design features, and high conductivity interconnect structures.
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require responsive changes in interconnection technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance-capacitance) interconnect pattern, particularly wherein submicron vias, contacts and trenches have high aspect ratios imposed by miniaturization.
Conventional semiconductor devices comprise a semiconductor substrate, typically doped monocrystalline silicon, and a plurality of sequentially formed interlayer dielectrics and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor xe2x80x9cchipsxe2x80x9d comprising five or more levels of metallization are becoming more prevalent as device geometry""s shrink to submicron levels.
A conductive plug filling a via hole is typically formed by depositing an interlayer dielectric on a conductive layer comprising at least one conductive pattern, forming an opening through the interlayer dielectric by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten (W). Excess conductive material on the surface of the interlayer dielectric is typically removed by chemical mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening in the interlayer dielectric and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact or via hole section in communication with an upper trench section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
High performance microprocessor applications require rapid speed of semiconductor circuitry. The control speed of semiconductor circuitry varies inversely with the resistance and capacitance of the interconnection pattern As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Miniaturization demands long interconnects having small contacts and small cross-sections. As the length of metal interconnects increases and cross-sectional areas and distances between interconnects decrease, the RC delay caused by the interconnect wiring increases. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As design rules are reduced to about 0.18 micron and below, e.g., about 0.15 micron and below, the rejection rate due to integrated circuit speed delays significantly reduces production throughput and increases manufacturing costs. Moreover, as line widths decrease electrical conductivity and electromigration resistance become increasingly important.
Cu and Cu alloys have received considerable attention as a candidate for replacing Al in interconnect metallizations. Cu is relatively inexpensive, easy to process, and has a lower resistively than Al. In addition, Cu has improved electrical properties vis-a-vis W, making Cu a desirable metal for use as a conductive plug as well as conductive wiring.
An approach to forming Cu plugs and wiring comprises the use of darnascene structures employing CMP, as in Teong, U.S. Pat. No. 5,693,563. However, due to Cu diffusion through interdielectric layer materials, such as silicon dioxide, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier metals include tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium-tungsten (TiW), tungsten (W), tungsten nitride (WN), Tixe2x80x94TiN, titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), tantalum silicon nitride (TaSiN) and silicon nitride for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the dielectric interlayer, but includes interfaces with other metals as well.
There are additional problems attendant upon conventional Cu interconnect methodology employing a diffusion barrier layer (capping layer). For example, conventional practices comprise forming a damascene opening in an interlayer dielectric, depositing a barrier layer such as TaN, lining the opening and on the surface of the interlayer dielectric, filling the opening with Cu or a Cu alloy layer, CMP, and forming a capping layer on the exposed surface of the Cu or Cu alloy. It was found, however, that capping layers, such as silicon nitride, deposited by plasma enhanced chemical vapor deposition (PECVD), exhibit poor adhesion to the Cu or Cu alloy surface. Consequently, the capping layer is vulnerable to removal, as by peeling due to scratching or stresses resulting from subsequent deposition of layers. As a result, the Cu or Cu alloy is not entirely encapsulated and Cu diffusion occurs, thereby adversely affecting device performance and decreasing the electromigration resistance of the Cu or Cu alloy interconnect member. Moreover, conventional PECVD silicon nitride capping layers have a density of about 2.62 g/cm3 and, hence, are not particularly effective as an etch stop layer during formation of interconnects for subsequent metallization levels.
In copending application Ser. No. 09/112,472 filed on Jul. 9, 1998, the adhesion problem of a PECVD silicon nitride capping layer to a Cu interconnect was addressed by initially treating the exposed surface with a hydrogen-containing plasma, forming a copper silicide layer on the treated surface and depositing a silicon nitride capping layer thereon. In copending U.S. Pat. No. 6,165,894 issued on Dec. 26, 2000, the adhesion problem of a silicon nitride capping layer to a Cu interconnect was addressed by treating the exposed surface with an ammonia-containing plasma and depositing a silicon nitride capping layer thereon. In copending U.S. Pat. No. 6,153,523 issued on Nov. 28, 2000, a method is disclosed wherein the exposed surface is treated with an ammonia-containing plasma and then depositing a silicon nitride capping layer under high density plasma conditions to achieve a density of about 2.67 to about 2.77 g/cm3. In copending application Ser. No. 09/497,850 filed on Feb. 4, 2000, a method is disclosed comprising treating the surface of a Cu or Cu alloy layer with a plasma containing nitrogen and ammonia, followed by depositing the capping layer in the presence of nitrogen in the same reaction chamber for improved adhesion of the capping layer to the copper interconnect. These techniques have been effect.
However, after further experimentation ad investigation, it was found that the surface of the Cu or Cu allow layer after plasma treatment to remove the copper oxide exhibited a discoloration, e.g., a black and/or green discoloration, indicating a poisoning and/or corrosion of the plasma treated Cu or Cu alloy surface prior to depositing the capping layer. This corrosion and/or poisoning problem at the interface between the Cu or Cu alloy interconnect and the capping layer, e.g., silicon nitride capping layer, adversely affects adhesion therebetween.
As design rules extend deeper into the submicron range, such as about 0.18 micron and under, e.g., about 0.15 micron and under, the reliability of the interconnect pattern becomes particularly critical. Therefore, the adhesion of capping or barrier layers to Cu interconnects and the accuracy of interconnects for vertical metallization levels require even greater reliability. Accordingly, there exists a need for methodology enabling the formation of encapsulated Cu and Cu alloy interconnect members for vertical metallization levels with greater accuracy and reliability. There exists a particular need for methodology enabling the formation of a capping layer on a Cu or Cu alloy interconnect with strong adhesion therebetween.
An advantage of the present invention is a method of manufacturing a semiconductor device having highly reliable Cu or Cu alloy interconnect members.
Another advantage of the present invention is a method of manufacturing a semiconductor device comprising a Cu or Cu alloy interconnect member having a silicon nitride capping layer tightly adhered thereto.
Additional advantages and other features of the present invention will be set forth in the description which follows and, in part, will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising sequentially: treating a surface of a copper (Cu) or Cu alloy with a plasma containing ammonia in a reaction chamber at a first pressure; reducing the first pressure to a second pressure of about 50 m Torr to about 100 m Torr over a period of about 30 seconds to about 60 seconds; introducing silane into the reaction chamber; and depositing a silicon nitride barrier layer on the surface of the Cu or Cu alloy layer in the reaction chamber.
Another aspect of the present invention is a method of manufacturing a semiconductor device, the method comprising sequentially: heating a reaction chamber to a temperature of about 300xc2x0 C. to about 420xc2x0 C.; purging the reaction chamber with nitrogen at the temperature of about 300xc2x0 C. to about 420xc2x0 C.; introducing a wafer into the chamber, the wafer containing a surface of a copper (Cu) or Cu alloy layer; treating the surface of the Cu or Cu alloy layer with and ammonia-containing plasma; and forming a barrier layer on the treated surface of the Cu or Cu alloy in the reaction chamber.
Embodiments of the present invention include gradually introducing silane into the reaction chamber, as in a plurality of short stages, until reaching a flow rate of at least about 150 sccm before initiating deposition of the silicon nitride barrier layer. Embodiments of the present invention further include initially purging the reaction chamber in a plurality of stages prior to introducing the wafer. Embodiments of the present invention further include forming an opening in an interlayer dielectric on a wafer, depositing an underlying diffusion barrier layer, such as TaN, lining the opening and on the interdielectric layer, depositing the Cu or a Cu alloy layer on the diffusion barrier layer filling the opening and over the interlayer dielectric, removing any portion of the Cu or Cu alloy layer beyond the opening by CMP, leaving an exposed surface oxidized, and conveying the wafer into the reaction chamber for processing in accordance with the present invention by treating the exposed surface of the Cu or Cu alloy layer with an ammonia-containing plasma; and depositing a silicon nitride barrier layer on the treated surface.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein embodiments of the present invention are described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
FIGS. 1-4 illustrate sequential phases of a method in accordance with an embodiment of the present invention.